IIT BHILAI PROJECT ASSOCIATE RECRUITMENT 2025: OPPORTUNITIES IN MEITY FUNDED RESEARCH PROJECT
IIT Bhilai Project Associate Recruitment 2025
Published: July 8, 2025 | By: rojgarclick.com
IIT Bhilai has opened an exciting opportunity for the youth of Chhattisgarh to work on a prestigious research project funded by the Ministry of Electronics and Information Technology (MeitY). The project focuses on developing high-precision interfacing circuits for capacitive-based sensors used in defence applications. Applications are invited for one position of Project Associate before 21 July 2025.
Project Overview
The project is led by Dr. Vivek Raghuvanshi (Assistant Professor, ECE Dept.) and Dr. Santosh Biswas (Professor, CSE Dept.) at IIT Bhilai. It aims to contribute to the defence sector by designing VLSI-based interfacing circuits for capacitive sensors. The project is funded by MeitY and spans 3 years. Initial appointment will be for 12 months, extendable based on performance.
Important Dates & Vacancy
- Application Deadline: 21 July 2025
- Total Vacancies: 1 (Project Associate)
Eligibility Criteria
- Diploma (ECE/EE or related) with minimum 4 years experience or
- B.E./B.Tech (ECE/EE) or M.Sc. (Electronics) with 2 years experience
- Maximum Age: 45 years
- Preference to candidates experienced in VLSI Design Tools and interested in Semiconductor Circuit Design
Salary & Benefits
- Monthly Salary: ₹45,000
- Eligible to register for PhD programme at IIT Bhilai as per institute norms (separate application required)
Application Process
Interested candidates must fill the application form (attached with official notice) and send it along with their updated resume to vivekr@iitbhilai.ac.in by the last date. Use the subject line: “Application for Project Associate”.
- Only applications with both the filled form and resume will be accepted.
- Sending only CV is not valid.
- Shortlisted candidates will be contacted for interview (no TA/DA provided).
Selection Process
- Shortlisting based on qualifications and experience
- Interview for shortlisted applicants
- If number of applicants is high, interview calls may be limited
- Final selection based on performance and decision of selection committee
Appointment is subject to satisfactory performance. Fellowship may be terminated with 30 days’ notice if performance is unsatisfactory.
Preparation Tips
- Review VLSI tools such as Cadence, Synopsys, or related software
- Brush up fundamentals of semiconductor design and interfacing circuits
- Highlight previous project experience in resume and during interview
- Prepare to discuss practical electronics, debugging, and research aptitude
To explore more such research jobs and opportunities, visit rojgarclick.com regularly. Stay updated and apply on time!
Post a Comment